Cellular Multiprocessor Technology Unisys Cellular MultiProcessing (CMP) is an open server architecture that combines powerful Intel processors with mainframe design concepts. Extremely modular and upgradeable, CMP permits high levels of scalability by adding processors, memory, or I/O modules as necessary to execute enterprise business processing workloads. Flexible Configuration through Partitioning Shared Memory Mainframe Reliability and Serviceability Enhanced Performance, Availability, and Manageability Architectural Highlights Flexible Configuration Through Partitioning Flexible Configuration Through Partitioning A CMP-based platform can be configured as one large symmetric multiprocessing (SMP) system or as multiple (up to eight) SMP partitions. Each partition operates under the control of an operating system; partitions can run the same or different operating systems. Unisys supports the Microsoft Windows NT/2000 and SCO UnixWare operating systems. Each partition can be configured with sufficient resources (processor, memory, and I/O modules) to execute its share of the total processing requirements efficiently. Through the use of our rich integrated maintenance system software running on a built-in maintenance interface processor, an administrator can control CMP partitioning -- configuring or reconfiguring the system to meet changing processing needs. CMP supports both static and dynamic partitioning. In a static partitioning environment, the administrator allocates system resources to a partition before a boot. These resources cannot be changed while the operating system is running. Dynamic partitioning provides the flexibility to automatically reallocate system resources to meet shifts in workload without interruptions to processing. Read about our collaboration with Microsoft on technical requirements for enhancing server performance, reliability and flexibility through dynamic partitioning on future versions of the Microsoft Windows Datacenter Server operating system - the version of Windows designed and positioned for the most mission critical environments. Shared Memory Partitions within a CMP-based platform can be configured to share nothing or to share a defined area of memory. When partitions share memory, applications running in them can communicate with each other by passing messages across the low-latency shared memory rather than a LAN connection. Mainframe Reliability and Serviceability CMP is designed with no single points of failure. A CMP-based platform provides built-in hardware redundancy and the ability to perform hot swaps on almost all field replaceable units. The platform can be separated into two independent electrical domains to protect against a possible power failure. The Integrated Maintenance System monitors the health of components and provides reporting, fault isolation, and recovery of most failures. Enhanced Performance, Availability, and Manageability Fully integrated software and hardware extensions to Windows NT/2000 are designed to enhance server scalability and general system performance, improve availability, and simplify the management of multi-server environments. Architectural Highlights A CMP-based platform is designed for maximum scalability and performance -- starting with memory and expanding outwards with low-latency interconnects, efficient processing modules, and PCI-based I/O modules. Processors. A processing element, or sub-pod, consists of four Intel IA-32 or four IA-64 bit CPUs, connected to a generous third-level cache to increase hit rates and maximize processor efficiency. 32-bit based sub-pods can coexist with 64-bit based sub-pods, permitting migration of applications from one Intel generation to another within the same cabinet. A maximum of eight sub-pods can be housed within a CMP-based platform. Memory. CMP is designed with state-of-the-art memory components -- advanced technology that allows access beyond the rated memory SDRAM speeds. Bandwidth is greatly enhanced by high levels of memory interleaving across the various areas of a Memory Storage Unit (MSU) and across different MSUs. An MSU can grow, in flexible increments, to 16 GB. A fully configured CMP-based platform can accommodate four MSUs (a maximum of 64GB). A hardware-supported memory directory facilitates highly efficient coherency. Interconnect. Designed with crossbar technology, CMP eliminates the bottlenecks associated with bus-based SMP architectures. A crossbar facilitates a very low-latency connection between the various components attached to it. Each crossbar can support two processing elements, or sub-pods, two Direct I/O Bridges (DIBs), and four Memory Storage Units (MSUs). In addition to passing messages between the components, the crossbar provides buffering, memory firewalls for memory hardware protection, and support for the memory directory. A fully configured CMP platform can support a maximum of four crossbars. I/O. Each Direct I/O Bridge provides three PCI standard buses, each supporting four PCI adapters. A fully configured CMP-based platform can support eight DIBs and 96 PCI adapters.